[Recent publications]

Journal Papers:

  1. Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak, “Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations.” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 34.11 (2015): 1822-1835.
  2. Chang, F-Y., R-S. Tsay, W-K. Mak, and S-H. Chen. “MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules.” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 32, no. 10 (2013): 1557-1568..
  3. Chen-Kang Lo, Mao-Lin Li, Jen-Chieh Yeh, Ren-Song Tsay, “Automatic Generation of High-speed Accurate TLM Models for Out-of-Order Pipelined Bus,” ACM Transactions on Embedded Computing Systems, 2013.
  4. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay,”A Distributed Timing Synchronization Technique for Parallel Multi-Core Instruction-Set Simulation,” ACM Transactions on Embedded Computing Systems, Feb. 2013.
  5. Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, and Ren-Song Tsay, “An Extended SystemC Framework for Efficient and Reliable HW/SW Co-Simulation,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17 Issue 2, April 2012
  6. Ching-Te Chiu , Tsun-Hsien Wang , Wei-Ming Ke , Chen-Yu Chuang , Jhih-Siao Huang , Wei-Su Wong , Ren-Song Tsay , and Cyuan-Jhe Wu, “Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform,” Journal of Signal Processing Systems, Springer, June 2010.

International Conference Papers:

  1. Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay, “A Data Effect Aware Microcomponent-Based Estimation Approach For Accurate System-Level Memory Device Power Evaluation,” SASIMI 2016, Outstanding Paper Award.
  2. Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay, “An Accurate Crowdsourcing-based Adaptive Fall Detection Approach Using Smart Devices,” ICHI 2016
  3. Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao and Ren-Song Tsay, “An Accurate and Flexible Early Memory System Power Evaluation Approach Using a Microcomponent Method,” CODES+ISSS 2016
  4. Chi-Kang Chen, Zih-Ci Huang, Ren-Song Tsay, “An Accurate Processor Power Estimation Approach based on Microcomponent Structure Analysis,” SASIMI 2015
  5. Hsin-I Wu, Li-chun Chen, Ren-Song Tsay, “An Effective Timing-Coherent Transactor Generation Approach for Mixed-level System Simulations,” SASIMI 2015
  6. Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay, “AROMA: A Highly Accurate Microcomponent-based Approach for Embedded Processor Power Analysis,” ASPDAC 2015
  7. Li-chun Chen, Hsin-I Wu, Ren-Song Tsay, “Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations,” ASPDAC 2015
  8. Shu-Yung Chen, Chien-Hao Chen and Ren-Song Tsay, “An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations”, DATE, 2014
  9. Chien-Min Lee, Chi-Kang Chen and Ren-Song Tsay, “A Basic-block Power Annotation Approach for Fast and Accurate Embedded Software Power Estimation,” VLSI-SoC 2013, pp.121~126
  10. Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay, “A Fast and Accurate Instruction-Oriented Processor Simulation Approach,” VLSI-DAT 2013
  11. Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay, “A Cycle Count Accurate TLM Bus Modeling Approach,” VLSI-DAT 2013
  12. Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee and Ren-Song Tsay, “A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations,” DATE 2013
  13. Bo-Han Zeng, Ren-Song Tsay and Ting-Chi Wang, “An Efficient Hybrid Synchronization Technique for Scalable Multi-Core Instruction Set Simulations,” ASPDAC 2013
  14. Fong-Yuan Chang, Ren-Song Tsay,  Wai-Kei Mak and Sheng-Hsiung Chen, “A Separation and Minimum Wire Length Constrained Maze Routing Algorithm Under Nanometer Wiring Rules,“ ASPDAC 2013
  15. Chen-Kang Lo, Mao-Lin Li, Jen-Chieh Yeh, Ren-Song Tsay, “Automatic TLM Model Generation for Cycle-Count-Accurate Bus Simulation,” the 2012 DAC Work-In-Progress Session
  16. Yu-Hung Huang, Hsin-I Wu, Ren-Song Tsay, “A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation,” DAC 2012
  17. Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Hong-Jie Huang, Jen-Chieh Yeh, Ren-Song Tsay, “A Formal Full Bus TLM Modeling for Fast and Accurate Contention Analysis,” The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012) Outstanding Paper Award
  18. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay,”A High-Parallelism Distributed Scheduling Mechanism for Multi-Core Instruction-Set Simulation,” DAC 2011
  19. Ren-Song Tsay, “From Academic Ideas to Practical Physical Design Tools,” International Symposium on Physical Design (ISPD), pp. 9~12, 2011.
  20. Chen Kang Lo, and Ren Song Tsay, “Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 341, 346, 2011
  21. Cheng-Yang Fu, Meng-Huan Wu, and Ren-Song Tsay, “A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 347~352, 2011
  22. Peng-Chih Wang, Meng-Huan Wu, and Ren-Song Tsay, “DOM: A Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 335~340, 2011
  23. Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen, “Cut-Demand Based Routing Resource Allocation and Consolidation for Routability Enhancement,” ASPDAC 2011
  24. Meng-Huan Wu, Fan-Wei Yu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay, “A Novel Timing Synchronization Method for Fast and Accurate Multi-Core Instruction-Set Simulators,” The 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)
  25. Meng-Huan Wu, Yi-Shan Lu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay, “Automatic Generation for Efficient Software TLM at Multiple Abstraction Layers,” The 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)
  26. Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, and Ren-Song Tsay, “Automatic Generation of Software TLM in Multiple Abstraction Layers for Efficient HW/SW Co-simulation,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1177~1184, 2010
  27. Kai-Li Lin, Chen-Kang Lo, and Ren-Song Tsay, “ Source-Level Timing Annotation for Fast and Accurate TLM Computation Model Generation,” ASPDAC 2010, pp. 235~240
  28. Fongyuan Chang, Ren-Song Tsay, and Wai Kei Mak, “How to Consider Shorts and Guarantee Yield Rate Improvement for Redundant Wire Insertion,” Proceedings of the 2009 International Conference on Computer-Aided Design, pp. 33~38, 2009
  29. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, and Ren-Song Tsay, “An Effective Synchronization Approach for Fast and Accurate Multi-core Instruction-set Simulation,” Proceedings of the seventh ACM international conference on Embedded software, 197~204, 2009, Grenoble, France
  30. Yi-Len Lo, Mao-Lin Li, and Ren-Song Tsay, ” Cycle Count Accurate Memory Modeling in System Level Design,CODES+ISSS’09, Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, October 11-16, 287~293, 2009, Grenoble, France
  31. Chen Kang Lo, and Ren Song Tsay, “ Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model,” in Proceedings of ASPDAC, pp.558-563, 2009
  32. Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, and Ren-Song Tsay, “A 100mhz Real-Time Tone Mapping Processor With Integrated Photographic and Gradient Compression in 0.13 Um Technolgy,” IEEE Workshop on Signal Processing Systems, 25~30, 2008.
  33. Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, and Ren-Song Tsay, “Design Optimization Of a Global/Local Tone Mapping Processor on Arm Soc Platform for Real-Time High Dynamic Range Video,”, 15th IEEE International Conference on Image Processing, pp. 1400~1403, 2008
  34. Ren-Song Tsay, “An Entrepreneurship Emulation Platform,” International Conference on Microelectronic Systems Education, 63~64, 2007

Domestic Conference Papers:

  1. Tzu-Yun Huang , Chien-Hao Chen , Hsin-I Wu , Chi-Kang Chen , Ren-Song Tsay, “Analytical Process Scheduling Optimization Using Scaling Factor for Heterogeneous Multi-core Systems” , 28th VLSI Design/CAD Symposium, Taiwan, August 2017
  2. Bo-Yu Huang, Hsin-I Wu, Chi-Kang Chen, Ren-Song Tsay, “VIRA: A Virtualization-Assisted Approach for Highly Efficient and Accurate Full-System Simulations”, 28th VLSI Design/CAD Symposium, Taiwan, August 2017.
  3. Kuo-Cheng Chin, Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay, “A Highly Reliable Fall Detection Approach Using Smart Devices on Real User Self-Adaptive Crowdsourcing-Based Framework,” 27th VLSI Design/CAD Symposium, Taiwan, August 2016
  4. Da-Yi Guo, Chi-Ting Hsiao, Chi-Kang Chen, Ren-Song Tsay, “An Microcomponent-based Approach for Accurate System-Level Memory Power Estimation,” 27th VLSI Design/CAD Symposium, Taiwan, August 2016
  5. Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay, “A Highly Accurate Fall Detection Approach Based on Crowdsourcing of Smart Devices,” Symposium on Digital Life Technologies 2016
  6. Wei-Hsin Chang, Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay, “AROMA: A Microcomponent-based Methodology for Accurate Embedded Processor Power Analysis,” 26th VLSI Design/CAD Symposium, Taiwan, August 2015
  7. Yun Chang, Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak “An Efficient Approach for Synchronization-Function-Level Parallel Multi-Core Instruction-Set Simulations,” 26th VLSI Design/CAD Symposium, Taiwan, August 2015
  8. Yu-Kang Hu, Chen-Kang Lo, Mao-Lin Li, Li-Chun Chen, Yi-Shan Lu,Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh, “Automatic Generation of Fast and Accurate TLM Models for Out-of-Order Pipelined Bus”, 26th VLSI Design/CAD Symposium, Taiwan, August 2015
  9. Hsiang-Yi Wu, Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay, “An Automatic Timing-Coherent-Based Transactor Generation Approach for Mixed-level Simulations,” 26th VLSI Design/CAD Symposium, Taiwan, August 2015
  10. Pei-Chia Patty Lin, Hsuan-Yi Lin, Evason Du, Ren-Song Tsay “An Instruction-Oriented Approach for Fast and Accurate Processor Simulation,” 25th VLSI Design/CAD Symposium, Taiwan, August 2014
  11. Shu-Yung Chen, Chien-Hao Chen, Cheng-Lin Tsai and Ren-Song Tsay, “An Efficient Deterministic Full-System Simulations with Activity-Sensitive Contention Delay Model,” 25th VLSI Design/CAD Symposium, Taiwan, August 2014
  12. Chien-Min Lee, Shin-yu Ho, and Ren-Song Tsay,”Fast and Accurate Embedded Software Power Estimation With A Basic-block Power Annotation,” 25th VLSI Design/CAD Symposium, Taiwan, August 2014
  13. Chen-Kang Lo, Kuan-Hsin Lee,  Mao-Lin Li, Ren-Song Tsay,Hsu-Yao Huang, Jen-ChiehYeh, “FSM Based Models for Fast and Accurate Out-of-Order Pipelined Bus Simulation,” 24th VLSI Design/CAD Symposium, Taiwan, August 2013
  14. Fan-Wei Yu, Wen-Jui Lee, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Ren-Song Tsay, “A Novel Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations,” 24th VLSI Design/CAD Symposium, Taiwan, August 2013
  15. Bo-Han Zeng, Chien-Hao Chen, Ren-Song Tsay, “A Efficient and Scalable Hybrid Synchronization Techniques for Multi-Core Instruction Set Simulations,” 24th VLSI Design/CAD Symposium, Taiwan, August 2013
  16. Yu-Hung Huang, Ching-Yu Chen, Yi-Shan Lu, Hsin-I Wu, and Ren-Song Tsay, “A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation,” 23rd VLSI Design/CAD Symposium, Taiwan, August 2012
  17. Mao-Lin Li, Shu-Yung Chen, Chen-Kang Lo, Li-Chun Chen, Ren-Song Tsay, Hong-Jie Huang, and Jen-Chieh Yeh, “An FSM-based modeling approach for fast and accurate bus contention simulation,“ 23rd VLSI Design/CAD Symposium, Taiwan, August 20
  18. Cheng-Yang Fu, Hsien-Lun Pai, Meng-Huan Wu, and Ren-Song Tsay, ”A Fast and Accurate Cache Coherence Simulation for Multi-Core Systems,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp.49~52
  19. Chen Kang Lo, Zih-Ci Huang, Li-Chun Chen, Meng-Huan Wu, and Ren Song Tsay, ”An Efficient and Cycle-Count-Accurate Processor for System-Level Simulation,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp. 53~56
  20. Peng-Chih Wang, Meng-Huan Wu, and Ren-Song Tsay, “A Data-dependency-Oriented Modeling Approach for Fast and Accurate Simulation of OS Preemptive Scheduling,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp.57~60
  21. Fong-Yuan Chang, Chi-Kang Chen, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen,”Early-Stage Routability Improvement,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp. 256~259
  22. Meng-Huan Wu, Hsin-I Wu, Peng-Chih Wang, Cheng-Yang Fu, and Ren-Song Tsay, “Distributed Scheduling for Parallel Instruction-Set Simulation of Multi-Core Systems,” 22nd VLSI Design/CAD Symposium, Taiwan, August 2011, pp. 585~588
  23. Meng-Huan Wu, Yu-Hung Huang, Cheng-Yang Fu, Peng-Chih Wang, and Ren-Song Tsay, “A Novel Synchronization Technique for Fast and Accurate Multi-core Instruction-set Simulation,” 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010 (Best paper nomination, 選為國科會優良論文)
  24. Kai-Li Lin, Pei-Jia Lin, Cheng-Kang Lo, and Ren-Song Tsay , “Fast and Accurate TLM Computation Model Generation Using Source-Level Timing Annotation,” 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010 (選為國科會優良論文)
  25. Yi-Len Lo, Li-Chun Chen, Mao-Lin Li, and Ren-Song Tsay, “A Cycle Count Accurate Timing Model for Fast Memory Simulation,” 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010

Patents:

Taiwan –

  1. 中華民國專利I507989 ,  黃子齊, 蔡仁松, 資源導向之嵌入式系統功率消耗分析方法METHOD OF RESOURCE-ORIENTED POWER ANALYSIS FOR EMBEDDED SYSTEM
  2. 中華民國專利 I507990, 吳孟寰, 蔡仁松, 「多核心指令集模擬之高平行化同步方法」A HIGH-PARALLELISM SYNCHRONIZATION APPROACH FOR MULTI-CORE INSTRUCTION-SET SIMULATION
  3. 中華民國專利I378356 , 吳孟寰, 傅正陽, 王鵬智, 蔡仁松, “多核心指令集之模擬方法與裝置,” METHOD AND DEVICE FOR MULTI-CORE INSTRUCTION-SET SIMULATION
  4. 中華民國專利, 利茂霖,羅振綱, 陳立君,黃鴻杰,葉人傑, 蔡仁松,「全匯流排之交易層級模擬方法以快速與精確的爭用分析/A Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis」2011. (pending)
  5. 中華民國專利,王鵬智, 吳孟寰, 蔡仁松, 「資料相依導向模型以有效率模擬作業系統先佔式排程之方法」, 2011. (pending)
  6. 中華民國專利, 吳孟寰, 蔡仁松, 「用以產生軟體交易層級模型之方法、系統及電腦可讀媒體」, 2010. (pending)
  7. 中華民國專利, 李建旻, 羅振綱, 吳孟寰, 蔡仁松, 「模擬處理器功率消耗之系統及其方法」, 2010. (pending)

United States –

  1. US Patent 9195788, Tzu-Chi Huang, Ren-Song, “Resource-oriented method of power analysis for embedded system.” U.S. Patent Application No. 14/016,305
  2. US Patent 8875081, Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak, “Systems and methods for designing and making integrated circuits with consideration of wiring demand ration.” U.S. Patent Application No. 14/486,723.
  3. US Patent 8549468 20110197174, Meng-Huan Wu and Ren-Song Tsay, “Method, System and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model,” U.S. Patent Application No. 12/701,810
  4. US Patent 8423343, Meng-Huan Wu and Ren-Song Tsay, “A High-Parallelism Synchronization Approach for Multi-Core Instruction-Set Simulation,” 2013.3.7
  5. US Patent 8,407,647, Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak, “Systems and methods for designing and making integrated circuits with consideration of wiring demand ration.”
  6. US Patent 8352924, Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, and Ren-Song Tsay, “Method and Device for Multi-Core Instruction-Set Simulation,” 10/21/2010
  7. US Patent 8336001, Fong-Yuan Chang, Wai-Kei Mak, and Ren-Song Tsay, ”Method For Improving Yield Rate Using Redundant Wire Insertion,” 05/05/2011
  8. US Patent 5461576 “Electronic Design Automation Tool for the Design of a Semiconductor Integrated Circuit Chip,” Oct. 24, 1995 (58 citations)
  9. US Patent 6009256 “Simulation/Emulation System and Method,” Dec. 28, 1999 (24 citations)
  10. US Patent 6134516 “Simulation Server System and Method,” Oct. 17, 2000 (13 citations)
  11. US Patent ,Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak, “Separation and minimum wire length constrained maze routing method and system.” U.S. Patent Application No. 14/496,420.
  12. US Patent 20120233410, Cheng-Yang Fu, Meng-Huan Wu and Ren-Song Tsay, “Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation,” 9/13/2012.
  13. US Patent, Peng-Chih Wang, Meng-Huan Wu and Ren-Song Tsay, “Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling,” 2011. (pending)
  14. US Patent, Chien-Min Lee, Chen-Kang Lo, Meng-Huan Wu, and Ren-Song Tsay, “System for Simulating Processor Power Consumption and Method of the Same,” 2010. (pending)
  15. US Patent 20100269103, Trent Lo, and Ren-Song Tsay, “Method, System and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model,” 10/21/2010.

Publications before 2005:

  1. Tsay, Ren-Song, “Exact Zero Skew”, in The Best of ICCAD – 20 Years of Excellence in Computer-Aided Design, Kluwer Academic Publishers, 2003.
  2. Tsay, Ren-Song, “TUTORIAL: Interconnect-Driven Performance Optimization for Deep Submicron Layout Systems” DAC, 1997.
  3. Kenneth D. Boese, Andrew B. Kahng, Ren-Song Tsay, “Scan Chain Optimization: Heuristic and Optimal Solutions”, Research Report UCLA (1994) (7 citations)
  4. Ho, J.-M., M. T. Ko and Ren-Song Tsay, “Assignment of Clock Driver”, Schloss Dagstuhl Seminar on Combinatorial Methods for VLSI/CAD, Oct. 1993 Germany.
  5. Chang, C.-C., J. Lee, M. Stabenfeldt and Ren-Song Tsay, “A Practical All-Path Timing-Driven Place and Route Design System”, Proc. Asia-Pacific Conf. on Circuits and Systems, 1994, pp. 560-563. (8 citations)
  6. Tsay, Ren-Song. An exact zero-skew clock routing algorithm. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12(2):2.42-249, 1993. (Best paper Award) (274 citations)
  7. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Timing-Driven System Partitioning by Constraints Decoupling Method,” Proc. 1993 IEEE Multichip Module Conf., pp. 164-169, March 1993. (5 citations)
  8. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Integer Programming Techniques for Multiway System Partitioning Under Timing and Capacity Constraints,” Proc. EDAC-Euroasic Conf., February 1993. (4 citations)
  9. Tsay, Ren-Song and I. Lin, “Robin Hood: A System Timing Verifier for Multi-Phase Level-Sensitive Clock Designs,” Proceedings of IEEE International Conference on ASICs, pp. 516-519, September 1992.
  10. Ho, J.-M. and Ren-Song Tsay, “Clock Tree Regeneration, ” Prof. IEEE GLS-VLSI’92, Feb. 1992.
  11. Tsay, Ren-Song and S. C. Chang, “Early Wirability Checking and 2-D Congestion-Driven Circuit Placement.” In International Conference on ASIC, pp. 50–53, 1992. (14 citations)
  12. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Performance-Driven Partitioning on Multi-Chip Modules,” Proc. Design Automation Conference, pp. 53-56, June 1992. (37 citations)
  13. Shih, M., E.S. Kuh, and Ren-Song Tsay, “System Partitioning for Multi-Chip Modules Under Timing and Capacity Constraints,” Proc. IEEE Multi-Chip Module Conference, pp. 123-126, March 1992. (2 citations)
  14. Vijayan, G. and Ren-Song Tsay. “A new method for floorplanning using topological constraint reduction,” IEEE. Trans. on CAD, 10(12):1494-1501, December 1991. (28 citations)
  15. Tsay, Ren-Song and J Koehl, “An analytic net weighting approach for performance optimization in circuit placement”, In Proc. ACM/IEEE Design Automation Conf., 1991, pp. 620-625. (53 citations)
  16. Tsay, Ren-Song, “Exact Zero Skew”, Proc. of International Conference on Computer Aided Design, pp. 336–339(1991). (159 citations)
  17. Tsay, Ren-Song and Ichiang Lin, “A system timing verifier for multiple-phase level-sensitive clock design,” Research Report RC 17272, IBM Yorktown, 1991.
  18. Shih, M., E.S. Kuh, and Ren-Song Tsay, “Performance-Driven System Partitioning on Multi-Chip Modules,” IBM Research Division Research Report RC 17315 (#76556), October 1991.
  19. Tsay, Ren-Song and Ernest Kuh, “A Unified Approach to Partitioning and Placement,” IEEE Trans. on Circuits and Systems, Vol. CAS-38, No. 5, pp. 521-533, May 1991. (58 citations)
  20. Tsay, Ren-Song, and E.S. Kuh, “A Unified Approach to Partitioning and Placement,” IBM Research Report RC-15482 (#68859), February 9, 1990.
  21. Vijayan, G. and Ren-Song Tsay, “Floorplanning by Topological Constraint Reduction”, ICCAD 1990: 106-109. 1989. (28 citations)
  22. Parng, T. and Ren-Song Tsay, “A New Approach to Sea-of-gates Global Routing,” Proc. IEEE International Conference on Computer-Aided Design, Nov. 1989, pp. 52-55. (18 citations)
  23. Daijavad, S., E. Polak, and S. Tsay, “A Combined Deterministic And Random Optimization Algorithm For The Placement Of Macro-Cells,” in International Workshop on Placement and Routing, Research Triangle Park, North Carolina, 1988.
  24. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “PROUD: A Sea-Of-Gates Placement Algorithm,” IEEE Design and Test of Computers, pp. 44-56, December 1988. (141 citations)
  25. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “Module Placement for Large Chips Based on Sparse Linear Equations,” International Journal of Circuit Theory and Applications, vol. 16, pp. 411-423, October 1988. (19 citations)
  26. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “PROUD: A Fast Sea-of-Gates Placement Algorithm,” Proceedings of 25th Design Automation Conference, pp. 318-323, June 1988. (135 citations)
  27. Daijavad, S., E Polak, and Ren-Song Tsay,” A combined deterministic and random optimization algorithm for the placement of macro-cells”, Technical Report No. UCB/ERL M87/86, 1987.
  28. Tsay, Ren-Song, E.S. Kuh, and C-P. Hsu, “PROUD: A Fast Sea-of-Gates Placement Algorithm,” UCB/ERL Memorandum M87/79, November 1987.
  29. Tsay, Ren-Song and E.S. Kuh, “A Unified Approach to Circuit Partitioning and Placement,” Proc. Princeton Conference on Information Sciences & Systems, pp. 155-160, March 1986. (6 citations)